Ipzz-040 〈Free Access〉

To achieve ecosystem adoption, IPZZ‑040 must align with emerging standards such as IEEE 802.3bs (400 GbE) and Optical Interconnect Consortium (OIC) specifications for on‑chip optics. Collaborative work with industry consortia will help define pin‑outs, testing protocols, and reliability benchmarks.

IPZZ‑040 is fabricated on a 300 mm SOI wafer with a 220 nm silicon device layer and a 2 µm buried oxide (BOX). The photonic components use a standard 193 nm immersion lithography flow, achieving 45 nm waveguide widths and 200 nm gaps for sub‑100 nm bending radii. The electronic transistors are built in a 7 nm FinFET node, co‑located via a “via‑first” integration scheme that places metal interconnects above the photonic layer without compromising optical mode confinement. IPZZ-040